Serial Rapidio Data Rate

Page 2 Functional Description RapidIO Dynamic Data Rate Reconfiguration Reference Design for Stratix IV GX Devices December 2010 Altera Corporation.

The RapidIO architecture is a high-performance packet-switched, interconnect technology. RapidIO supports messaging, read/write and cache coherency semantics.

LogiCORE IP Serial RapidIO v5.6 – SRIO Gen 1.3 with extensions for Gen 2 -5G line rate Support For the Serial RapidIO Gen 2 Xilinx LogiCORE IP, please click here.

Serial RapidIO to TI 6482 Digital Signal Processor Reference Design Programs the SRIO MegaCore function to any Serial RapidIO MegaCore 1x or 4x lane, data rate.

Serial RapidIO only specifies thes e rates for both the 1x and 4x ports. data rate, which means it is not possible to identify the best setting by data rate.

1. The Emergence of High-Speed Serial Interfaces. With the ever-increasing demand for higher data bandwidth, wired interfaces have increased their clock rates and.

Serial RapidIO Gen 2; a Flow Control Extensions Specification was released that provides congestion control for medium-rate data plane applications using the.

Serial RapidIO LogiCORE IP

LogiCORE IP Serial RapidIO v5.6 – SRIO Gen 1.3 with extensions for Gen 2 -5G line rate Support

For the Serial RapidIO Gen 2 Xilinx LogiCORE IP, please click here.

The LogiCORE IP Serial RapidIO Endpoint solution, designed to RapidIO Gen 1.3 specification with Gen 2 -5G line rate support, comprises of a highly flexible and optimized Serial RapidIO Physical Layer core and a Logical I/O AND Transport Layer core. This core is designed to ensure predictable timing, thereby significantly reducing engineering time investment and allowing resources to be focused on user-specific application logic.

The RapidIO Logical I/O and Transport Layer core and the RapidIO Physical Layer core, provide a complete Serial RapidIO protocol stack.  Additionally, a highly optimized and configurable buffer design is included with these cores to implement a Serial RapidIO endpoint. While a modular IP design approach provides flexibility to enable ease of customization, the Xilinx tool chain automates generation of the serial endpoint on an FPGA by using these building block IP cores through a configurable and easy-to-use graphical user interface.